1. Field of the Invention
The present invention relates to the semiconductor manufacturing process, and more particularly, to a method of forming junction isolation to isolate active elements.
2. Description of the Related Art
All non-trivial integrated electronics involve connection of isolated devices through specific electrical connection paths. The device isolation scheme is therefore critical when fabricating integrated circuits.
Shallow and deep trench isolations have been introduced to the fabrication of devices for isolation between device elements. The trenches are formed by removing part of a silicon substrate with dry etching. Then, using deposition, dielectric material is filled in the trenches, and the surface profile of the trenches is planarized by CMP (chemical mechanical polishing).
Depending on the etching process, refilling process and CMP steps, the fabrication has some drawbacks. For instance, the manufacturing process is complex and costly. In addition, voids are easily formed in the trench during deposition. Also, crystal defects such as dislocation inevitably occur during the trench process. Such defects seriously affect device reliability and yield.
The object of the present invention is to provide a method of forming junction isolation in a semiconductor substrate.
Another object of the present invention is to provide a method of forming junction isolation to isolate active elements.
In order to achieve these objects, a method of forming junction isolation to isolate active elements is provided. A semiconductor substrate having a plurality of active areas and an isolation area between active areas is provided. A first gate structure is formed on part of the substrate located in the active areas and, simultaneously, a second gate structure serving as a dummy gate structure is formed on the substrate located in the isolation area. A first doped region is formed in the substrate located at two sides of the first gate structure and two sides of the second gate structure. A bottom anti-reflection layer is formed on the substrate, the first gate structure and the second gate structure. Using anisotropy etching, part of the bottom anti-reflection layer is etched back to expose the second gate structure. The second gate structure is removed to expose the substrate. A second doped region serving a junction isolation region is formed in the substrate located in the isolation area. The bottom anti-reflection layer is removed.
The present invention improves on the prior art in that the present method uses the self-alignment of the gate structures to define the isolation area and the active area. Then, after removing the dummy gate structure, suitable ions are implanted into the substrate located in the isolation area to form a junction isolation region in the substrate. Thus, the invention can avoid voids and defects in the substrate, thereby raising reliability and yield, and ameliorating the disadvantages of the prior art.